TM 11 5895-1096-40
f. Divide-by-Three-Counter. This counter develops the
inverter to the input on pin 1.
The feedback resistor R1
biases the gate to operate as a linear amplifier.
digit strobe, in conjunction with the multiplexer, to begin the
Interconnected with components Y1, C1, C2, and R2, the gate
sequence necessary to encode Natural Binary Coded Decimal
forms an oscillator that provides the 512 KHz clock signal to
(NBCD) data from the CODE SELECTOR switches.
the divider U2.
g. Multiplexer. The multiplexer is a sequential switch
(2) Divide-by 512 Counter (U2).
U2 is a
which allows transmission of data from two or more sources
multistage binary ripple counter. The ninth output 09 is used
over a common path by using different time intervals for
to produce a 29 division (512 512 = 1 KHz) of the input clock
different signals. The selector (SEL) pulse produced by the
DIVIDE-BY-FOUR counter, directs the DIVIDE-BYTHREE
frequency. The Q9 output of U2 is connected to the clock
counter as to which channel should be the source of the
trigger input of U3A, U3B and U5B.
encoding data.
The multiplexer is thus instructed to
b. Divide-by-Four Counter (U5A and U5B). This stage
sequentially data from the CODE SELECTOR switches. The
is used as a ripple counter and is comprised of an
multiplexer also generates the End-of-Word (EOW) pulse at
interconnected dual J/K flip-flop.
the end of each sequence.
(1) The KHz clock signal from U2, caused U5B to
h. Delay Flip-Flop. The delay flip-flop synchronizes the
change output states with such positive-going pulse, and the
time-multiplexed data and the EOW pulse.
signal at its (pin 14) output is a 500 Hz square wave
(1) The EOW pulse is applied to the DIVIDE-
(measured at TP2).
The output is used to drive the
BYFOUR counter causing the counter to stutter for one code
multiplexer and USA.
bit and creating the 13-bit code work only when the MESSAGE
(2) The 500 Hz clock signal from U5B, causes
switch is in its SO2-STOP position.
USA to change output states with each positive-going pulse,
(2) The NRZ, or complement CODE output is
and the signal at its Q (pin 2) output is a 250 Hz square wave
selected by the PHASE switch and applied to the NRZ TO
(measured at TPI). The output is used to drive the multiplexer
BIPHASE CONVERTER.
and the divide-by-three stages.
(3) The operation described in (1) and (2) above
i. NRZ to Biphase Converter. This converter converts
occurs when the MESSAGE switch is in its SO1-START
the NRZ code output to its biphase equivalent.
Biphase
position which holds the J/K inputs of U5B HI. When the
coding consists of a true bit and complement bit for each bit of
switch is in its SO2-STOP position, the EOW pulse from U3B-
NRZ code (i.e., the first bit of biphase code for each NRZ bit
12 is applied to the J/K inputs. This is a negative logic pulse
indicates the code information and the following bit is always
and inhibits the divide-by-four counter for one clock period,
the opposite or complement).
which causes the counter to stutter for one code bit and the
j. Word Counter.
This counter initiates the code
multiplexer to repeat the first bit of each code word.
generation, controlled by counting the number of code words,
(4) Since the counter advances on the positive
when the MODULATION switch is activated.
inputs and the outputs that are utilized are the complements,
When manual mode of operation is selected code generation
or negative logic, the counter actually counts in a descending
is limited. When continuous mode is selected continuous
order with respect to the binary value of its output.
code generation occurs.
k. Buffer. This stage provides the low impedance drive
c. Divide-by-Three Counter (U7A, U7B, UIC).
This
signal for the code and EOW sync pulses.
stage is comprised of a dual J/K flip-flop, and an exclusive OR
l. 14 VDC Power Supply. The test set operates from a
wired so as to provide a divide-by-three function.
power source of 120 VAC which is converted by the power
supply to a regulated + 14 VDC output to all circuits.
(1) The two Q outputs from U7B-15 and U7A-1
m. Probe Power Supply.
The probe power supply
provide the tens and units strobes respectively, and sequence
provides regulated dc power to the external amplifier probe
through the three combinations as shown in table 2-1.
and assembly.
(2) Hundreds strobe decoder U1C, decodes the 0-
n. AC/DC Isolation. This stage protects the 14 VDC
0 state of U7B-15 and U7A-1 and provides the hundreds
power supply in the event the probe power supply is
strobe as shown in table 2-2.
improperly loaded. It also separates the 19.25 MHz signal
d. Code Selector Switches. (fig. 2-2). To generate
(picked up by the external probe) riding on the DC supplied to
the serial code, a time division multiplexing concept is used.
the probe amplifier.
Each of the front panel CODE SELECTOR switches is
o. Probe and Amplifier Assembly.
This external
sequentially strobed, and the resulting NBCD data from each
assembly is used to check the adjustment of the AN/GRA-114
switch is sequentially selected producing the 12-bit (13 bit if in
transmitter modulator.
S02-STOP position) serial code.
Each NRZ code word is
subdivided into three numbers and each number contains four
binary bits of NBCD data.
Each selector switch is a 10
2-3. Circuit Description
position rotary switch with one common pole as shown in table
2-3. Each of the four outputs from each selector switch is
a. 1 KHz Clock Oscillator (U1 and U2).
logically OR'ed by a diode arrangement, located on the
(1) 512 KHz Crystal Oscillator, UIA. With pin 2 of
selector switches, to the four inputs (8, 4, 2, and 1) of the
the exclusive "OR" held high, this gate functions as an
multiplexer.
2-2
