TM 32-5811-025-14&P
5-8. Parallel-to-Serial Converter CCA A1.
(See figure FO-1.) Parallel-to-serial converter CCA A1 receives the logic states set in DIAGNOSTIC TEST
switches S1 thru S17 via signal lines DDL0 thru DDL8, SAS1 thru SAS5, SAS7, SAS11, and MOD. The CCA also
receives the logic states wired into rotary VERIFICATION TEST switch S18.
A multiplexer consisting of U13 thru U19 selects between the diagnostic test inputs and the verification test
inputs in response to the setting of TEST MODE switch S19 via the mode-select signal line (edge card connector, XA1
pin 61). When switch S19 is high, the verification test inputs are selected. When switch S19 is low, the diagnostic test
inputs are selected. The multiplexer outputs are routed to a 24-bit parallel-to-serial converter consisting of U10 thru U12.
Dual voltage-controlled multivibrator U7A generates the 500-kHz clock signal used to clock the parallel-to-serial
converter, and the CCAs control flip-flops U3A and U3B and counter U9. The parallel-to-serial converter's load pulse is
generated from the U7A clock output by flip-flops U3B, U3A, and U2B. Once the parallel-to-serial converter (U10 thru
U12) is loaded with data from the multiplexer (U13 thru U19), serial data are clocked out of the converter and routed to
data driver U6B. Driver U6B then outputs the data to the RF processor under test via the DT DATA OUT and DT DATA
OUT signal lines. As the data are clocked out of the converter, counter U9 counts the clock pulses.
At the end of the data board transmission, U2A and U3B are cleared. The U3B pin 8 high output is applied to
U3A and U2B clear inputs, enabling these flip-flops to be clocked. U3A pin 6 goes low then high, causing U2B pin 8 to
be clocked low. This low clears U1B (thereby enabling U2A and U3B), and places the 24-bit shift register in the load
parallel inputs mode of operation, and clears counter U9. The shift register loads the switch data from multiplexer U13
thru U19. Clocked by the 500-kHz signal, U3A generates a second low-then-high transition at pin 6, causing U2B pin 8 to
be clocked high. The U2B pin 8 high transition clocks U2A pin 5 high, places the shift register in the shift mode of
operation, and enables counter U9. The next 500-kHz clock pulse clocks U3B pin 9 high and pin 8 low. The U3B pin 9
high transition enables clock output gate U6A and the ENAP input of counter U9, thereby enabling U9 to count clock
pulses. The U3B pin 8 low transistion clears U3A and U2B, holding the shift register in the shift mode of operation, and
enables the shift register clock input, allowing data to be clocked out by the 500-kHz clocks, disabling the strobe output of
U5A.
The eighth clock pulse counted by counter U9 causes U9 pin 11 to go high. The high is applied to U4A and,
inverted by U8C, to the clock input of U1B as a high-to-low transition. The low output of U1B pin 9 disables U4A.
5-5
