TM 32-5811-025-14&P
The 16th clock pulse counted by counter U9 causes U9 pin 11 to go low. The low is applied to U4A, which
disables the gate, and, inverted by U8C, the low is applied to the U1B clock input as a low-to-high transition, which
causes U1B pin 9 to go high.
The 24th clock pulse counted by counter U9 causes U9 pin 11 to go high. The U9 pin 11 high input to U4A,
combined with the high U1B pin 9 input, causes gate U4A to clear flip-flops U2A and U3B. When cleared, the U3B pin 9
low output disables clock gate U6A and counter U9. The U3B pin 8 high output enables U3A and U2B, disables the shift
register clock input, and causes U5A and U2B, disables load pulse on the DT STROBE OUT and DT STROBE OUT
lines.
While clock gate U6A is enabled, U6A outputs 24 500-kHz clock pulses on the DT CLK OUT and DT CLK OUT
lines. Twenty-four command data bits are outputted through gate U6B on the DT DATA OUT and DT DATA OUT lines.
Multiplexer output U13 pin 4 is routed to gate U5B to generate the modulation signal on the DT MODE OUT and
DT MODE OUT lines.
5-9. Power Supplies.
(See figures FO-2 and FO-3.) The power supplies of the RF processor test set consist of emi filter FL1, power
switch S20, circuit breaker CB1, interlock relays K1, K2, and power relay K3, ac fan B1, and various power modules.
Input 115-V ac, 3- , 400-Hz power is routed through emi filter FL1 to power relay K3. When switch S20 is set to
the POWER ON position, power relay K3 is energized and the ac input is routed through circuit breaker CB1 to the RF
processor under test and to the RF processor test set power supply fan. With relay K3 energized, relays K1 and K2
energize and dc voltage from the power supply is supplied (via J7) to the RF processor being tested. Since the POWER
ON indicator lamps are connected between the +15-V and -15-V outputs of the power supply (via dropping resistor R1),
the POWER ON indicator provides a rough indication of the status of these voltages.
The power supplies receive their ac power input from CB1. They consist of switching preregulator modules
80ASP12S1 and 80ASP12S2, HF generator module 80G90W40, and output modules 5TR50 and 15TR13. The
switching preregulator receives the 115-V ac, 1- , 400-Hz input voltage from circuit breaker CB1 and provides an 80-V
dc output voltage to the HF generator. The HF generator accepts the 80-V dc input and provides a 40-V ac output
voltage to drive the various output modules. The 5TR50 output module accepts the 40-V ac input voltage and produces
a +5-V dc output for use by the RF processor under test and the circuitry of the RF processor test set. The 15TR13
output modules provide +15 V dc and -15 V dc for use by the RF processor under test. The indicator lamp contained in
power switch S20 is activated by the +15-V dc and -15-V dc module outputs.
5-6
