TM 32-5811-025-14&P
Table 6-2. DIAGNOSTIC TEST Switch Settings
RF SWITCHES
DELAY LINE BITS
BITE
PROC
VERIFI-
CATION
S8
S6
S4
S3
S2
S1
D8
D7
D6
D5
D4
D3
D2
D1
TEST-TEST
&9
&7
SELECT
1
H
H
L
H
H
H
L
L
L
L
L
L
L
L
L
H
2
H
H
L
H
H
H
L
L
L
L
L
L
L
L
L
H
3
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
4
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
5
H
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
6
H
H
H
L
H
L
H
L
L
L
L
L
L
L
L
H
7
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
H
8
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
H
Table 6-3. Logic States
VERIFICATION TEST-TEST
MODULATION
SELECT position
(Pin 3 of J6)
1
H
2
L
3
H
4
L
5
H
6
L
7
H
8
L
6-9
